In the mid-1990's, a new class of error correcting codes called “Turbo codes” was introduced [3]. Turbo codes achieve performance, typically measured in BER (bit error rate), very close to a long sought-after limit known as the Shannon bound. The decoding algorithms used in Turbo codes have since been generalized into a class of decoding algorithms based on factor graphs [17, 6]. These algorithms are commonly referred to as message-passing algorithms. Turbo-like codes which employ message-passing algorithms are generally referred to as iterative decoders.
An important general form of message passing algorithms is the sum-and-product algorithm [9], which implements probability propagation on a graph. The sum-and-product algorithm is a very general algorithm which describes decoders for many codes, including trellis codes, LDPC (low-density parity check) codes, block product codes, BCJR (Bahl, Cocke, Jelinek, Raviv) codes [2], and Turbo codes. The sum-and-product algorithm also describes algorithms used in artificial intelligence.
There has been great interest in implementing iterative decoders, but conventional digital implementations are often complex and demand expensive resources. Analog circuits for iterative decoding have been proposed and demonstrated by various researchers in recent years [10, 7, 12, 13, 14, 8, 15, 18]. CMOS (Complementary Metal Oxide Semiconductor) circuits are of particular interest for some applications because they can be implemented in ordinary so-called “plain vanilla” CMOS processes, which are low-cost compared to high-end alternatives such as BiCMOS and SiGe. CMOS analog decoders can also be more easily integrated with other CMOS components for single-chip receiver solutions.
In many cases, analog decoders offer significant advantages over digital designs. For example, the operations required for implementing the sum-and-product or BCJR algorithms can be implemented in analog decoders with fewer transistors. Analog circuits also require significantly fewer wire connections between components. Such efficient use of space allows parallel circuit implementations to enable decoding operations to occur completely in parallel, which thereby provides for high data throughput.
Analog decoders are also intrinsically low-power, and eliminate the need for high speed analog-to-digital (A/D) conversion in a receiver front-end. A typical A/D converter by itself consumes a significant amount of power and silicon real-estate. An analog decoder may thus be thought of as an information A/D converter, specially designed to convert coded analog channel information into decoded bits.